U.S. Pat. No. 6,936,885 B2 describes an NAND-type flash memory device and methods of fabricating the same. A surface of a semiconductor substrate is patterned by parallel strips of insulating regions that delimit the active areas of the device. Wordlines are arranged transversally to the striplike active areas and cross the insulating regions. Rows of memory cell transistors that are connected in series are limited on both ends by select transistors, which are connected to a source line and to drain contact plugs, respectively. The drain contact plugs are applied to the drain regions and are connected to bitlines that are arranged in superior levels above the memory cell array. In one variant of the described method, a spacer is formed on sidewalls of a string selection line pattern, a plurality of wordline patterns, and a ground selection line pattern. An etch stop layer and a first interlayer insulating layer are sequentially formed on the entire surface of the resultant structure and are successively patterned to form a slit-type common source line contact hole. At the same time, a drain contact hole exposing a drain region of the respective string is formed. Barrier insulating layers and conformal barrier metal layers are formed on sidewalls of the common source line contact hole and the drain contact hole. The metal layer is also applied to the bottom. A metal layer filling the common source line contact hole and the drain contact hole is formed on the entire surface of the resultant structure, and the metal layer and the barrier metal layers are etched to form planar metal patterns filling the common source line contact hole and the drain contact hole. A second interlayer insulating layer is formed on the entire surface of the resultant structure and patterned to form a bitline contact hole exposing a respective drain contact plug and a source contact hole exposing a predetermined region of the common source line.